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smsc EMC2112 datasheet revision 0.88 (11-20-09) datasheet product features EMC2112 rpm-based linear fan controller with hardware thermal shutdown general description the EMC2112 is an smbus, closed-loop, rpm-based fan driver with hardware (hw) thermal shutdown and reset controller. the EMC2112 offers a single high side fan driver capable of sourcing up to 600ma from a 5v supply. the EMC2112 utilizes beta compensation (an implementation of the bjt or transistor model for thermal diodes) and resist ance error correction (rec) to accurately monitor up to three (3) external temperature zones. these f eatures allow great accuracy for cpu substrate thermal diodes on multiple process geometries as well as with discrete diode-connected transistors. both beta compensation and rec can be disabled on the EMC2112 to maintain accuracy when monitoring amd thermal diodes. the EMC2112 provides a stand-alone hw thermal shutdown block. the hw thermal shutdown logic can be configured for a few common configurations based on the strapping level of the shdn_sel pin on the pcb. the hw thermal shutdown point can be set in 1c increments by using a discret e resistor connected to the trip_set pin. the EMC2112 also provides 5v supply ?power good? function with a threshold of 4.5v. this function is provided on the reset pin. applications ? notebook computers ? desktop computers ? embedded applications features ? closed-loop rpm-based fan controller ? 1% accuracy with external clock input ? 3% accuracy with internal clock ? internal clock can be used as a source ? aging fan detection ? integrated linear fan driver ? 600ma drive capability ? hw thermal shutdown (sys_shdn ) ?1 c incremental set points for thermal shutdown ? cannot be disabled by software ? provides rese t function (reset ) on 5v supply ? up to three (3) remote thermal zones ? 1 c accuracy (60 c to 100 c) ? 0.125 c resolution ? designed to support 45nm, 65nm, and 90nm cpu diodes using bjt and transistor model ? eliminates temperature offset due to series resistance from pcb traces and thermal ?diode? ? operates from single 3.0 - 3.6v supply ? 5v supply for linear fan driver and reset generator ? smbus 2.0 and i 2 c compatible ? user selectable smbus address using pull-up resistor on addr_sel pin ? supports block read and write functionality ? available in 20-pin, 4x4 qfn lead-free rohs compliant package
rpm-based linear fan controller with hardware thermal shutdown datasheet revision 0.88 (11-20-09) 2 smsc EMC2112 datasheet copyright ? 2009 smsc or its subsidiaries. all rights reserved. circuit diagrams and other information relating to smsc products are included as a means of illu strating typical applications. consequently, complete information sufficient for construction purposes is not necessarily given. although the information has been checked and is believed to be accurate, no re sponsibility is assumed for inaccuracies. smsc reserves the right to make changes to specifications and product descriptions at any time without notice. contact your local sm sc sales office to obtain the latest specifications before placing your product order. the provision of this information does not convey to the purchaser of the described semicond uctor devices any licenses under any patent rights or other intellectual property rights of smsc or others. all sales are expressly conditional on your agreement to the te rms and conditions of the most recently dated version of smsc's standard terms of sale agreement dated before the date of your order (the "terms of sale agreement"). the pro duct may contain design defects or errors known as anomalies which may cause the product's functions to deviate from published specifications. anomaly sheets are availab le upon request. smsc products are not designed, intended, authorized or warranted for use in any life support or other application where product failure could cause or contribute to personal injury or severe property damage. any and all such uses without prior written approval of an officer of smsc and further testing and/or modification will be fully at the risk of the customer. copies of this document or other smsc literature, as well as the terms of sale agreement, may be obtained by visiting smsc?s website at h ttp://www.smsc.com. smsc is a registered trademark of standard microsystem s corporation (?smsc?). product names and compan y names are the trademar ks of their respective holders. smsc disclaims and excludes any and all war ranties, including without li mitation any and all implied warranties of merchantabil ity, fitness for a particular purpose, title, and against infringement and the like, and any and all warranties arising from any cou rse of dealing or usage of trade. in no event shall smsc be liab le for any direct, incidental, i ndirect, special, punitive, or cons equential damages; or for lost data, profits, savings or revenues of any kind; regardless of the form of action, whether based on contrac t; tort; negligence of smsc or others; strict liability; breach of w arranty; or otherwise; whether or not any remedy of buyer is h eld to have failed of its essential purpose, and whether or not smsc has been advised of the possibility of such damages. reel size is 4,000 pieces this product meets the halogen maximum concentration values per iec61249-2-21 for rohs compliance and environm ental information, please visit www.smsc.com/rohs please contact your smsc sales representative for additional documentation related to this product such as application notes, anomaly sheets, and design guidelines. ordering number package features EMC2112-bp-tr 20-pin qfn 4mm x 4mm (lead-free rohs compliant) three external diodes. high side fan driver w/ rpm based fan speed control algorithm. reset generator. hardware set critical temperature limit ordering information:
rpm-based linear fan controller with hardware thermal shutdown datasheet smsc EMC2112 3 revision 0.88 (11-20-09) datasheet table of contents chapter 1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 chapter 2 pin layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1 pin layout for EMC2112. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.2 pin description for em c2112 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 chapter 3 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.2 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.3 smbus electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 chapter 4 system management bus interface protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.1 system management bus interface protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.1.1 smbus start bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.1.2 smbus address and rd / wr bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.1.3 smbus data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.1.4 smbus ack and nack bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.1.5 smbus stop bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.1.6 smbus time-out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.1.7 smbus and i 2 c compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.2 smbus protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.2.1 write byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.2.2 read byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.2.3 send byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.2.4 receive byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.2.5 block write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.2.6 block read protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.2.7 alert response address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 9 chapter 5 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.1 fan control modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.2 rpm-based fan speed control algorithm (fsc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.2.1 programming the rpm-based fan speed control al gorithm . . . . . . . . . . . . . . . . . . . . . 22 5.3 tachometer measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.3.1 stalled fan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.3.2 aging fan or invalid drive detectio n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.3.3 clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.4 spin up routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.5 ramp rate control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.5.1 temperature bypass of ramp rate control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.6 watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.6.1 power up operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.6.2 continuous operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.7 high side fan driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.7.1 overcurrent limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.8 internal thermal shutdown (tsd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.9 critical/thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.9.1 trip_set pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.9.2 shdn_sel pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.9.3 internal hw_shdn signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.10 5v reset controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
rpm-based linear fan controller with hardware thermal shutdown datasheet revision 0.88 (11-20-09) 4 smsc EMC2112 datasheet 5.11 temperature monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.11.1 dynamic averaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.11.2 resistance error correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1 5.11.3 beta compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.11.4 digital averaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.12 diode connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.12.1 diode faults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 chapter 6 register set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.1 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.1.1 lock entries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.2 temperature data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.3 critical/thermal shutdown temperature registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6.4 tripset voltage register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 6.5 ideality factor registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 6.6 beta configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 6.7 rec configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 6.8 critical temperature limit registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 6.9 configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 6.10 configuration 2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 6.11 interrupt status register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 6.12 error status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 6.12.1 tcrit status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 6.13 fan status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 6.14 interrupt enable register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 6.15 fan interrupt enable register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 6.16 limit registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 6.17 fan setting register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 6.18 fan configuration 1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 6.19 fan configuration 2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 6.20 gain register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 6.21 fan spin up configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 6.22 fan max step register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 6.23 fan minimum drive register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6.24 valid tach count register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6.25 fan drive fail band registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 6.26 tach target registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 6.27 tach reading registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 6.28 software lock register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 6.29 product features register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 6.30 product id register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 6.31 manufacturer id register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 6.32 revision register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 chapter 7 typical operating curves. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 chapter 8 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 8.1 EMC2112 package drawings - 20-pin qfn 4mm x 4mm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 8.2 package marking information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 chapter 9 datasheet revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
rpm-based linear fan controller with hardware thermal shutdown datasheet smsc EMC2112 5 revision 0.88 (11-20-09) datasheet list of figures figure 1.1 EMC2112 block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 2.1 EMC2112 pin diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 4.1 smbus timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 5.1 EMC2112 system diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 5.2 spin up routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 5.3 ramp rate control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 5.4 EMC2112 critical/thermal shutdown block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 5.5 hw_shdn operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 5.6 5v reset controller timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 5.7 diode connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 8.1 EMC2112 package drawing - 20-pin qfn 4mm x 4mm . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 figure 8.2 EMC2112 package dimensions and notes - 20-pin qfn 4mm x 4mm . . . . . . . . . . . . . . . . 63 figure 8.3 EMC2112 pcb footprint - 20-pin qfn 4mm x 4mm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 figure 8.4 EMC2112 package markings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
rpm-based linear fan controller with hardware thermal shutdown datasheet revision 0.88 (11-20-09) 6 smsc EMC2112 datasheet list of tables table 2.1 pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 2.2 pin types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 3.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 3.2 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 3.3 smbus electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 4.1 addr_sel pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 4.2 protocol format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 4.3 write byte protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 4.4 read byte protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 4.5 send byte protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 4.6 receive byte protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 4.7 block write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 4.8 block read protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 4.9 alert response address protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 5.1 fan controls active for operating mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 5.2 trip_set resistor setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 5.3 shdn_sel pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 5.4 dynamic averaging behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 6.1 EMC2112 register set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 6.2 temperature data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 6.3 temperature data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 6.4 critical/thermal shutdown temperature registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 6.5 critical / thermal shutdown data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 6.6 tripset voltage register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 6.7 ideality factor registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 6.8 ideality factor look-up table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 6.9 substrate diode ideality factor look-up table (bjt model) . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 6.10 beta configuration registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 6.11 beta compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 6.12 rec configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 6.13 tcrit limit registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 6.14 configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 6.15 configuration 2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 6.16 fault queue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 6.17 conversion rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 6.18 interrupt status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 6.19 error status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 6.20 fan status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 6.21 interrupt enable register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 6.22 fan interrupt enable register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 6.23 limit registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 6.24 fan setting register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 6.25 fan configuration 1 register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 6.26 range decode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 6.27 minimum edges for fan ro tation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 6.28 update time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 6.29 fan configuration 1 register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 6.30 derivative options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 6.31 error range options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 6.32 gain register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 6.33 gain decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 6.34 fan spin up configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
rpm-based linear fan controller with hardware thermal shutdown datasheet smsc EMC2112 7 revision 0.88 (11-20-09) datasheet table 6.35 drive_fail_cnt[1:0] bit decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 6.36 spin level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 6.37 spin time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 6.38 fan max step register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 6.39 minimum fan drive register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 6.40 valid tach count register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 6.41 fan drive fail band registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 6.42 tach target registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 6.43 tach reading registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 6.44 software lock register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 6.45 product features register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 6.46 addr_sel pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 6.47 shdn_ch pin configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 6.48 product id register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 6.49 manufacturer id register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 6.50 revision register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 9.1 customer revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
rpm-based linear fan controller with hardware thermal shutdown datasheet revision 0.88 (11-20-09) 8 smsc EMC2112 datasheet chapter 1 block diagram figure 1.1 EMC2112 block diagram analog mux external temp diodes internal temp diode 11 bit adc ext. temp registers register set and logic dp1 smclk smdata ext temp limit registers alert voltage reading dn1 dp2 / dn3 dn2 / dp3 trip_set critical / thermal shutdown logic high side fan driver 8-bit dac fan (2) vdd_5v (2) smbus slave protocol sys_shdn bandgap reference automatic fan control algorithm tach monitor reset generator reset tach voltage -> temperature converison vdd_3v vdd_5v addr_sel shdn_sel clk anti- parallel diode
rpm-based linear fan controller with hardware thermal shutdown datasheet smsc EMC2112 9 revision 0.88 (11-20-09) datasheet chapter 2 pin layout 2.1 pin layout for EMC2112 2.2 pin description for EMC2112 figure 2.1 EMC2112 pin diagram table 2.1 pin description pin name function type 1 vdd_3v 3.3v supply voltage power 2 dn1 negative (cathode) analog input for external diode 1 aio 3 dp1 positive (anode) analog input for external diode 1 aio 4 dn2 / dp3 negative (cathode) analog input for external diode 2 and positive (anode) analog input for external diode 3 aio 1 2 3 4 6 7 8 9 5 10 15 14 13 12 20 19 18 17 11 16 EMC2112 20-pin qfn 4mm x 4mm gnd dn1 dp1 vdd_3v dn2 / dp3 dp2 / dn3 trip_set shdn_sel smdata alert reset gnd clk smclk vdd_5v vdd_5v fan fan tach sys_shdn addr_sel
rpm-based linear fan controller with hardware thermal shutdown datasheet revision 0.88 (11-20-09) 10 smsc EMC2112 datasheet the pin type are described in ta b l e 2 . 2 . all pins labeled with (5v) are 5v tolerant. 5 dp2 / dn3 positive (anode) analog input for external diode 2 and negative (cathode) analog input for external diode 3 aio 6 shdn_sel determines hw shutdown temperature channel dit 7 trip_set voltage input to determine hw shutdown threshold temperature aio 8 sys_shdn active low critical system shutdown output od (5v) 9 reset push-pull, active low reset output do 10 addr_sel selects smbus address dit 11 clk tachometer clock input di (5v) tachometer clock output do 12 alert open drain, active low interrupt. requires external pull-up resistor od (5v) 13 gnd ground connection power 14 smdata smbus data input/output - requires external pull- up resistor diod (5v) 15 smclk smbus clock input - requires external pull-up resistor di (5v) 16 vdd_5v 5v supply input for the linear fan driver. both vdd_5v pins should be connected to same 5v supply. power 17 fan linear fan drive signal. both fan pins should be connected together. ao 18 fan linear fan drive signal. both fan pins should be connected together. ao 19 vdd_5v 5v supply input for the linear fan driver. both vdd_5v pins should be connected to same 5v supply. power 20 tach tachometer input from fan di (5v) table 2.2 pin types pin type description power this pin is used to supply power or ground to the device. di digital input - this pin is used as a digital input. this pin is 5v tolerant. ao analog output - this pin is used as an output for analog signals. aio analog input / output - this pin is used as an i/o for analog signals. table 2.1 pin description (continued) pin name function type
rpm-based linear fan controller with hardware thermal shutdown datasheet smsc EMC2112 11 revision 0.88 (11-20-09) datasheet do push / pull digital output - this pin is used as a digital output. it can both source and sink current. diod digital input / open drain output - this pin is used as a digital i/o. when it is used as an output, it is open drain and requires a pull-up resistor. this pin is 5v tolerant. dio digital input / output - this pin is used as a digital i/o. it is push-pull and can sink or source up to 8ma. od open drain digital output - this pin is used as a digital output. it is open drain and requires a pull-up resistor. this pin is 5v tolerant. dit tri-stated digital input - this pin is a digital input that supports 3 logic levels at the input: logic high, logic low, or high impedance (open). table 2.2 pin types (continued) pin type description
rpm-based linear fan controller with hardware thermal shutdown datasheet revision 0.88 (11-20-09) 12 smsc EMC2112 datasheet chapter 3 electrical specifications 3.1 absolute maximum ratings these ratings are absolute maximum values. exceedin g these values or operating at these values for an extended period of time may cause permanent damage to the device. note 3.1 all voltages are relative to ground. note 3.2 the package power dissipation specification assumes a thermal via design consisting of four 20mil vias connected to the ground pl ane with a 2.6mm x 2.6mm thermal landing. note 3.3 junction to ambient ( ja ) is dependent on the design of t he thermal vias. without thermal vias and a thermal landing, the ja is approximately 60c/w including localized pcb temperature increase. 3.2 electrical specifications table 3.1 absolute maximum ratings voltage on vdd_5v pins and 5v tolerant pins (see table 2.1 ) -0.3 to 6.5 v voltage on vdd_3v pin -0.3 to 4 v voltage on fan pins -0.3 to vdd_5v + 0.3 v voltage on any other pin to gnd -0.3 to vdd_3v + 0.3 v package power dissipation 0.9 up to t a = 85c note 3.2 w junction to ambient - 20 pin qfn ( ja ) note 3.3 40 c/w operating ambient temperature range 0 to 85 c operating die temperature range 0 to 125 c storage temperature range -55 to 150 c esd rating, all pins, hbm 2000 v table 3.2 electrical specifications vdd_3v = 3v to 3.6v, vdd_5v = 4.6v - 5.5v, t a = 0c to 85c all typical values at t a = 27c unless otherwise noted. characteristic symbol min typ max unit conditions dc power 3.3v supply voltage v dd_3v 33.33.6v 5v supply voltage v dd_5v 4.6 5 5.5 v supply current from vdd_3v pin i dd3 0.750 1.6 ma fan driver enabled 4 conversions / sec supply current from vdd_5v pin i dd5 50 ua fan driver enabled
rpm-based linear fan controller with hardware thermal shutdown datasheet smsc EMC2112 13 revision 0.88 (11-20-09) datasheet external temperature monitors temperature accuracy 0.25 1 c 60c < t diode < 100c 30c < t die < 85c ( note 3.4 ) 0.5 2 c 0c < t diode < 125c, 0c < t die < 115c ( note 3.4 ) temperature resolution 0.125 c diode decoupling capacitor c filter 2700 pf connected across external 2n3904 diode or amd diode ( note 3.5 ) resistance error corrected r series 100 ohm series resistance in dp and dn lines internal temperature monitor temperature accuracy 1 2 c ( note 3.4 ) temperature resolution 0.125 c reset generator reset voltage v reset 4.3 4.4 4.5 v v dd_5v rising edge 3v < v dd_3v < 3.6v hysteresis v reset 100 mv time delay t reset 220 ms high side fan driver output high voltage from 5v supply v oh_5v vdd_5 v - 0.4 vi source = 600ma, vdd_5v = 5v fan drive current i source 600 ma overcurrent limit i over 1500 ma momentary current drive at startup for < 2 seconds dc short circuit current limit i short 800 ma sourcing current, thermal shutdown not triggered, fan_out = 0v short circuit delay t dfs 2s output capacitive load c load 100 uf esr on c load r esr 02ohm rpm-based fan controller tach range tach 480 16000 rpm table 3.2 electrical specifications (continued) vdd_3v = 3v to 3.6v, vdd_5v = 4.6v - 5.5v, t a = 0c to 85c all typical values at t a = 27c unless otherwise noted. characteristic symbol min typ max unit conditions
rpm-based linear fan controller with hardware thermal shutdown datasheet revision 0.88 (11-20-09) 14 smsc EMC2112 datasheet note 3.4 t die refers to the internal die temperature and may not match t a due to self heating of the device. the internal temperature sensor will return t die . note 3.5 contact smsc for application notes and guidelines when measuring gpu processor diodes and cpu processor diodes. note 3.6 the alert , sys_shdn , smdata, and smclk pins will not glitch low upon power up when pulled to vdd or another voltage. 3.3 smbus electrical specifications rpm control accuracy tach 0.25 0.5 % external oscillator 32.768khz tach 0.5 1 % internal oscillator 40c < t die < 100c thermal shutdown thermal shutdown threshold tsd th 150 c thermal shutdown hysteresis tsd hyst 50 c smbus and digital i/o pins output high voltage v oh vdd _3v-0.4 v 4 ma current drive output low voltage v ol 0.5 v 4 ma current sink table 3.3 smbus electrical specifications vdd_3v = 3v to 3.6v, vdd_5v = 4.6 to 5.5v, t a = 0c to 85c typical values are at t a = 27c unless otherwise noted. characteristic symbol min typ max units conditions smbus interface input high voltage v ih 2.0 v input low voltage v il 0.8 v input high/low current i ih / i il -1 1 ua input capacitance c in 5pf output low sink current 4 ma smdata = 0.5v smbus timing clock frequency f smb 10 400 khz spike suppression t sp 50 ns table 3.2 electrical specifications (continued) vdd_3v = 3v to 3.6v, vdd_5v = 4.6v - 5.5v, t a = 0c to 85c all typical values at t a = 27c unless otherwise noted. characteristic symbol min typ max unit conditions
rpm-based linear fan controller with hardware thermal shutdown datasheet smsc EMC2112 15 revision 0.88 (11-20-09) datasheet bus free time start to stop t buf 1.3 us setup time: start t su:sta 0.6 us setup time: stop t su:stp 0.6 us data hold time t hd:dat 0.6 6 us data setup time t su:dat 0.6 72 us clock low period t low 1.3 us clock high period t high 0.6 us clock/data fall time t fall 300 ns min = 20+0.1c load ns clock/data rise time t rise 300 ns min = 20+0.1c load ns capacitive load c load 400 pf per bus line table 3.3 smbus electrical specifications (continued) vdd_3v = 3v to 3.6v, vdd_5v = 4.6 to 5.5v, t a = 0c to 85c typical values are at t a = 27c unless otherwise noted. characteristic symbol min typ max units conditions
rpm-based linear fan controller with hardware thermal shutdown datasheet revision 0.88 (11-20-09) 16 smsc EMC2112 datasheet chapter 4 system management bus interface protocol 4.1 system management bus interface protocol the EMC2112 communicates with a host controller, such as an smsc sio, through the smbus. the smbus is a two-wire serial communication prot ocol between a computer host and its peripheral devices. a detailed timing diagram is shown in figure 4.1 . stretching of the smclk signal is supported, however the EMC2112 will not stretch the clock signal. 4.1.1 smbus start bit the smbus start bit is defined as a transition of th e smbus data line from a logic ?1? state to a logic ?0? state while the smbus clock line is in a logic ?1 ? state. when the EMC2112 detects an smbus start bit, it will disable the bc-link protocol circ uitry and communicate using the smbus protocol 4.1.2 smbus address and rd / wr bit the smbus address byte consists of the 7-bi t client address followed by a -bit rd / wr indicator. if this rd / wr bit is a logic ?0?, then the smbus host is writing data to the client device. if this rd / wr bit is a logic ?1?, then the smbus host is reading data from the client device. the slave address is determined at power up by the pin-state of the addr_sel pin as shown in table 4.1 . figure 4.1 smbus timing diagram table 4.1 addr_sel pin configuration addr_sel pin state smbus slave address ?0? 0101_111xb ?high z? 0111_101xb ?1? 0101_110xb smdata smclk t buf p s s - start condition p - stop condition p s t high t low t hd:sta t su:sto t hd:sta t hd:dat t su:dat t su:sta t fall t rise
rpm-based linear fan controller with hardware thermal shutdown datasheet smsc EMC2112 17 revision 0.88 (11-20-09) datasheet 4.1.3 smbus data bytes all smbus data bytes are sent most significant bit first and composed of 8-bits of information. 4.1.4 smbus ack and nack bits the smbus client will acknowledge all data bytes that it receives (as well as the client address if it matches and the ara address if the atf_int# pin is asserted). this is done by the client device pulling the smbus data line low after the 8th bit of each byte that is transmitted. the host will nack (not acknowledge) the data rece ived from the client by holding the smbus data line high after the 8th data bit has been sent. 4.1.5 smbus stop bit the smbus stop bit is defined as a transition of the smbus data line from a logic ?0? state to a logic ?1? state while the smbus clock line is in a logic ?1? state. when the EMC2112 detects an smbus stop bit, and it has been communicating with the smbus pr otocol, it will reset its client interface and prepare to receive further communications. 4.1.6 smbus time-out the EMC2112 includes an smbus time-out feature. following a 30ms period of inactivity on the smbus, the device will time-out and reset the smbus interface. the timeout can be disabled by setting the dis_to bit in the configuration 2 register. 4.1.7 smbus and i 2 c compliance the major difference between smbus and i2c devices is highlighted here. for complete compliance information refer to the smbus 2.0 specification. 1. minimum frequency for smbus communications is 10khz. 2. the client protocol will reset if t he clock is held for longer than 30ms. 3. the slave protocol will reset if both the clock and data lines are held high for longer than 150us. 4. i 2 c devices do not support the alert response addre ss functionality (which is optional for smbus). 5. the block read and block write protocols are only compliant with i 2 c data formatting. they do not support smbus formatting for bl ock read and block write protocols. 4.2 smbus protocols the EMC2112 is smbus 2.0 compatible and support s send byte, read byte, receive byte and write byte as valid protocols as shown below. it will re spond to the alert response address protocol but is not in full compliance. all of the below protocols use the convention in ta b l e 4 . 2 . table 4.2 protocol format data sent to device data sent to the host # of bits sent # of bits sent
rpm-based linear fan controller with hardware thermal shutdown datasheet revision 0.88 (11-20-09) 18 smsc EMC2112 datasheet 4.2.1 write byte the write byte is used to write one byte of data to the registers as shown below table 4.3 : 4.2.2 read byte the read byte protocol is used to read one byte of data from the registers as shown in table 4.4 . 4.2.3 send byte the send byte protocol is used to set the internal address register pointer to the correct address location. no data is transferred during the send byte protocol as shown in ta b l e 4 . 5 . 4.2.4 receive byte the receive byte protocol is used to read data from a register when the internal register address pointer is known to be at the right location (e.g. set via send byte). this is used for consecutive reads of the same register as shown in ta b l e 4 . 6 . table 4.3 write byte protocol start slave address wr ack register address ack register data ack stop 1 -> 0 0111_101 0 0 xxh 0 xxh 0 0 -> 1 table 4.4 read byte protocol start slave address wr ack register address ack start slave address rd ack register data nack stop 1 -> 0 0111_101 0 0 xxh 0 0 -> 1 0111_101 1 0 xxh 1 0 -> 1 table 4.5 send byte protocol start slave address wr ack register address ack stop 1 -> 0 0111_101 0 0 xxh 0 0 -> 1 table 4.6 receive byte protocol start slave address rd ack register data nack stop 1 -> 0 0111_101 1 0 xxh 1 0 -> 1
rpm-based linear fan controller with hardware thermal shutdown datasheet smsc EMC2112 19 revision 0.88 (11-20-09) datasheet 4.2.5 block write protocol the block write is used to write multiple data byte s to a group of contiguous registers as shown in table 4.7 . it is an extension of the write byte protocol. 4.2.6 block read protocol the block read is used to read multiple data by tes from a group of contig uous registers as shown in table 4.8 . it is an extension of the read byte protocol. 4.2.7 alert response address the alert output can be used as a processor interr upt or as an smbus alert when configured to operate as an interrupt. when it detects that the alert pin is asserted, the host will send the alert response address (ara) to the general address of 0001_100xb. all devices with active interrupts will respond with their client address as shown in table 4.9 . the EMC2112 will respond to the ara in the following way if the alert pin is asserted. 1. send slave address and verify that full slav e address was sent (i.e. the smbus communication from the device was not prematurely stopped due to a bus contention event). 2. set the mask bit to clear the alert pin. table 4.7 block write protocol start slave address wr ack register address ack register data ack 1 ->0 0111_101 0 0 xxh 0 xxh 0 register data ack register data ack . . . register data ack stop xxh 0 xxh 0 . . . xxh 0 0 -> 1 table 4.8 block read protocol start slave address wr ack register address ack start slave address rd ack register data 1->0 0111_101 0 0 xxh 0 1 ->0 0111_101 1 0 xxh ack register data ack register data ack register data ack . . . register data nack stop 0 xxh 0 xxh 0 xxh 0 . . . xxh 1 0 -> 1 table 4.9 alert response address protocol start alert response address rd ack device address nack stop 0 -> 1 0001_100 1 0 0111_1010b 1 1 -> 0
rpm-based linear fan controller with hardware thermal shutdown datasheet revision 0.88 (11-20-09) 20 smsc EMC2112 datasheet chapter 5 general description the EMC2112 monitors up to three (3) external temperature channels. each of the external temperature channels can employ bot h beta compensation (an implement ation of the bjt or transistor model for thermal diodes) and resistance error correct ion for use with thermal diodes while the third channel is hardwired to measure a discrete diode connected npn or pnp transistor. the temperature data is available over a standard 2-wire serial interface using smbus read commands. the temperature monitoring is described in more detail in section 5.11, "temperature monitoring" . the EMC2112 includes a closed-loop rpm-based fan control algorithm for each fan driver. the host writes the desired fan speed into a register of the EMC2112 via the smbus and the integrated fan controller will maintain the fan at the desired speed using fan speed f eedback from the tach output from a 3-wire fan. the fan cont rol algorithm controls an integrat ed 5v, 600ma, linear fan driver. the EMC2112 provides the system with a hardwar e based critical/thermal shutdown function. this critical/thermal shutdown function in tegrates critical signals from bo th the cpu and power supply and the analog circuitry to monitor a specific temperat ure channel based on the s ystem configuration. the critical/thermal shutdown temperature threshold is configured on the pcb through a simple discrete resistor. the critical/thermal shutdown function is described in more detail in section 5.9, "critical/thermal shutdown" . an example of a typical system configuration for the EMC2112 is provided in figure 5.1 . figure 5.1 EMC2112 system diagram EMC2112 dp1 dn1 dp2 / dn3 dn2 / dp3 cpu thermal diode 3.3v smclk smdata alert vdd_3v tach 3.3v kbc addr_sel gnd tachometer reset 3.3v 5v vdd_5v(2) fan(2) 3.3v sys_shdn shdn_sel clk_in 32.768khz clock vref trip_set 3.3v 3.3v optional anti- parallel diode
rpm-based linear fan controller with hardware thermal shutdown datasheet smsc EMC2112 21 revision 0.88 (11-20-09) datasheet 5.1 fan control modes of operation the EMC2112 has two modes of operation for the fan driver. each mode of operation uses the ramp rate control and spin up routine. 1. direct setting mode - in this mo de of operation, the user direct ly controls the fan drive setting. updating the fan driver setting register (see section 6.17 ) will instantly update the fan drive. ramp rate control is optional and enabled via the en_rrc bits. ? whenever the direct setting mode is enabled, t he current drive will be changed to what was last written into the fan driver setting register. 2. fan speed control mode (fsc) - in this mo de of operation, the user determines a target tachometer count and the drive sett ing is automatically updated to achieve this target speed. the algorithm uses the spin up routine and has user definable ramp rate controls. 5.2 rpm-based fan speed control algorithm (fsc) the EMC2112 includes a rpm-based fan spe ed control algorithm for the fan driver. this fan control algorithm uses proportional, integral, and derivative terms to automatically approach and maintain the system?s desired fan speed to an accuracy directly propor tional to the accuracy of the clock source. the desired tachometer co unt is set by the user inputting t he desired number of 32.768khz cycles that occur per fan revolution. this is done by se tting the tach target register. the user may change the target count at any time. the user may also set the target count to ffh in order to disable the fan driver for lower current operation. table 5.1 fan controls active for operating mode direct setting mode fsc mode fan driver setting (read / writ e) fan driver setting (read only) edges[1:0] edges[1:0] (fan configuration) - range[1:0] (fan configuration) update[2:0] (fan configuration) update[2:0] (fan configuration) level (spin up configuration) level (spin up configuration) spinup_time[1:0] (spin up configuration) spinup_time[1:0] (spin up configuration) fan max step fan max step - fan minimum drive valid tach count valid tach count - tach target (read / write) tach reading tach reading - drive_fail_cnt[1:0] and drive band fail registers
rpm-based linear fan controller with hardware thermal shutdown datasheet revision 0.88 (11-20-09) 22 smsc EMC2112 datasheet for example, if a desired rpm rate for a 2-pole fan is 3000 rpms, then the user would input the hexidecimal equivalent of 1296 (51h in the tach targ et register). this number represents the number of 32.768khz cycles that would occu r during the time it takes the fan to complete a single revolution when it is spinning at 3000rpms. the EMC2112?s rpm-based fan speed control algor ithm has programmable configuration settings for parameters such as ramp-rate control and spin up conditions. th e fan driver autom atically detects and attempts to alleviate a stalled/stuck fan condition while also asserting the alert pin. the EMC2112 works with fans that oper ate up to 16,000 rpms and provide a valid tachometer signal. the fan controller will function either with an externally supplied 32.768khz clock source or with it?s own internal 32khz oscillator depending on the required accuracy. 5.2.1 programming the rpm-base d fan speed control algorithm the rpm-based fan speed control algorithm is disabled upon device power up. the following registers control the algorithm. the EMC2112 fan control register s are pre-loaded with defaults that will work for a wide variety of fans so only the ta ch target register is required to set a fan speed. the other fan control registers can be used to fine-tune the algorithm behavior based on application requirements. note that steps 1 - 6 are optional and need only be performed if the default settings do not provide the desired fan response. 1. set the spin up configuration register to the spin up level and spin time desired. 2. set the fan step register to the desired step size. 3. set the fan minimum drive register to the minimum drive value that will maintain fan operation. 4. set the update time, and edges options in the fan configuration register. 5. set the valid tach count register to the highest tach count that indicates the fan is spinning. 6. set the tach target register to the desired tachometer count. 7. enable the rpm-based fan speed control algorithm by setting the en_algo bit. 5.3 tachometer measurement the tachometer measurement circ uitry is used in conjunction with the rpm-based fan speed control algorithm to update the fan driver output. addition ally, it can be used in direct setting mode as a diagnostic for host based fan control. this method monitors the tach signal in real ti me. it constantly updates the tachometer measurement by reporting the nu mber of clocks between a user programm ed number of edges on the tach signal. the tachometer measurement provides fast res ponse times for the rpm-based fan speed control algorithm and the data is presented as a count va lue that represents the fan rpm period. when this method is used, all fan target values must be input as a count value for proper operation. application note: the tachometer measurement method works independently of the drive settings. if the device is put into direct setting and the fan drive is set at a le vel that is lower than the fan can operate (including zero drive), then the ta chometer measurement may signal a stalled fan condition and assert an interrupt. 5.3.1 stalled fan a stalled fan is detected if the tach counter exce eds the user-programmable valid tach count setting then it will flag the fan as stalled and trigger an interrupt. if the rpm-based fan speed control algorithm is e nabled, the algorithm will automatically attempt to restart the fan until it detects a valid tachometer level or is disabled.
rpm-based linear fan controller with hardware thermal shutdown datasheet smsc EMC2112 23 revision 0.88 (11-20-09) datasheet the fan_stall status bit indicates that a stalled fan was detected. this bi t is checked conditionally depending on the mode of operation. ? whenever the direct setting mode is enabled or wh enever the spin up routine is enabled, the fan_stall interrupt will be masked for the duration of the programmed spin up time (see section 6.21 ) to allow the fan an opportunity to reac h a valid speed without generating unnecessary interrupts. ? in direct setting mode with the tachometer me asurement using the tach period measurement method, whenever the tach reading register value exceeds the valid tach count register setting, the fan_stall status bit will be set. ? when using the rpm-based fan speed control algorithm, the stalled fan condition is checked whenever the update time is met and the fan drive setting is updated. it is not a continuous check. 5.3.2 aging fan or in valid drive detection this is useful to detect aging fan conditions (where the fan?s natural maximum speed degrades over time) or incorrect fan speed settings. the EMC2112 co ntains circuitry that det ects that the programmed fan speed can be reached by the fa n. if the target fan speed canno t be reached within a user defined band of tach counts at maximum drive then the drive_fail status bits are set and the alert pin is asserted. 5.3.3 clock source the clk pin can be configured as an input for the em c2112 or as an output to drive additional devices with the internally generated tachometer clock (see section 6.9 ). when the clk pin is configured as an input to the EMC2112, then a 32.768khz clock must be provided. this clock is used to by the tachometer measurement circuitry and will directly affect the accuracy of this measurement. when the clk pin is configured as an output, then it will be driven at the same frequency as the internal tachometer clock. 5.4 spin up routine the EMC2112 also contains programmable circuitry to control the spin up behavior of the fan driver to ensure proper fan operation. the spin up routine is initiated in direct setting mode when the setting value changes from 00h to anything else. when the fan speed control algorithm is enabled, the spin up routine is initiated under the following conditions when the tach period measurement method of tach measurement is used: 1. the tach target register value changes from a value of ffh to a value that is less than the valid tach count (see section 6.24 ). 2. the rpm-based fan speed control algorithm?s m easured tach reading register value is greater than the valid tach count setting. when the spin up routine is operating, the fan driv er is set to full scale (optional) for one quarter of the total user defined spin up time. for the remaining spin up time, the fan driver output is set a a user defined level (30% through 65% drive). after the spin up routine has finished, the em c2112 measures the tach signal. if the measured tach reading register value is higher than the valid tach count register setting, the fan_spin status bit is set and the spin up routine will automatically attempt to restart the fan. figure 5.2 shows an example of the spin up routine in response to a programmed fan speed change based on the first condition above.
rpm-based linear fan controller with hardware thermal shutdown datasheet revision 0.88 (11-20-09) 24 smsc EMC2112 datasheet 5.5 ramp rate control the fan driver can be configured with automatic ramp rate control. ramp rate control is accomplished by adjusting the drive output se ttings based on the maximum fan step register settings and the update time settings. if the rpm-based fan speed control algorithm is us ed, then this ramp rate control is automatically used. the user programs a maximum step size fo r the fan drive setting and an update time. the update time varies from 100ms to 1.6s while the fan drive maximum step can vary from 1 count to 31 counts. when a new fan drive setting is entered, the delta fr om the next fan drive setting and the previous fan drive setting is determined. if this delta is greater than the max step settings, then the fan drive setting is incrementally adjusted every 100ms to 1.6s as de termined by the update time until the target fan drive setting is reached. see figure 5.3 . figure 5.2 spin up routine 100% (optional) 30% through 65% algorithm controlled drive fan step spin up time ? of spin up time update time target count changed target count reached new target count prev target count = ffh check tach
rpm-based linear fan controller with hardware thermal shutdown datasheet smsc EMC2112 25 revision 0.88 (11-20-09) datasheet 5.5.1 temperature bypass of ramp rate control as an optional feature, the ramp rate control f unctionality can be disabled if any of the measured temperature channels exceed their respective high li mits. in this mode, once the high limit has been exceeded, the ramp rate controls are removed which allows the fan to move instantly to the programmed drive setting (using the fsc or in manual mode). 5.6 watchdog timer the EMC2112 contains an internal watchdog time r for the fan driver. the watchdog timer monitors the smbus traffic for signs of activity and works in two different modes based upon device operation. these modes are power up operation and continuous operation as described below. for either mode of operation, if fo ur (4) seconds elapse without activity detected by the host, then the watchdog will be triggered and the following will occur: 1. the watch status bit will be set which will cause the alert pin to be asserted. 2. the fan driver will be set to full scale drive. it will remain at full scale drive until it is disabled. application note: when the watchdog timer is activated the fan speed control algorithm is automatically disabled. disabling the watchdog will not automa tically set the fan drive nor re-activate the fan speed control algorithm. this must be done manually. figure 5.3 ramp rate control previous setting next desired setting max step max step update time update time setting changed
rpm-based linear fan controller with hardware thermal shutdown datasheet revision 0.88 (11-20-09) 26 smsc EMC2112 datasheet 5.6.1 power up operation the watchdog timer only starts immediately after power-up and once it has been triggered or deactivated will not restart (however can be co nfigured to operate in continuous operation) in the power up operation, the watchdog timer is disabled by any of the following actions: 1. writing the fan setting register will disable the watchdog timer. 2. enabling the rpm-based fan speed control algorithm by setting the en_algo bit will disable the watchdog timer. the fan driver will be set based on the rpm-based fan speed control algorithm. 3. changing the watchdog operatin g mode by setting the wd_en bit. writing any other configuration registers will not disable the watchdog timer upon power up. 5.6.2 continuous operation when configured to operate in continu ous operation, the watchdog timer will start immediately. it can be disabled by any access (read or write) to th e smbus register set. upon completion of smbus activity, the watchdog timer is reset and restarted. 5.7 high side fan driver the EMC2112?s integrates a 5v, 600ma, linear high side fan driver to directly drive a 5v fan. by fully integrating the linear fan driver, the typical require ment for the discrete pass device and other external linearization circuitry is completely eliminated. 5.7.1 overcurrent limit the high side fan driver contains circuitry to allow for significant over current levels to accommodate transient conditions on the fan pins. the over cu rrent limit is dependent upon the output voltage with the limit dropping as the voltage nears 0v. if the fan driver current detects a short-circuit condition for longer than 2 seconds, then the i_short status bit is set and an interrupt generated. additionally, the high side fan driver will be disabled for 8 seconds. after this 8 second time has elapsed, it will be allowed to restart invoking the spin up routine before returning to its previous drive setting. application note: if the fsc algorithm is active, then it will generate errant spin_fail interrupts during the 8 second time that the f an driver is held off. 5.8 internal thermal shutdown (tsd) the EMC2112 contains an internal thermal shutdown ci rcuit that monitors the internal die temperature. if the die temperature exceeds the thermal shutdown threshold (see ta b l e 3 . 2 ), then the following will occur: 1. the high side fan driver is di sabled. it will remain disabled unt il the internal temperature drops below the threshold temperature minus 50c. 2. the tsd status bit is set. 3. the sys_shdn pin is asserted. 5.9 critical/thermal shutdown the EMC2112 provides a har dware critical/thermal shut down function for systems. figure 5.4 is a block diagram of this critical/thermal shutdown fu nction. the critical/thermal shutdown function in
rpm-based linear fan controller with hardware thermal shutdown datasheet smsc EMC2112 27 revision 0.88 (11-20-09) datasheet the EMC2112 consists of both analog and digital func tions. it accepts configuration information from the fixed states of the shdn_sel pin as described in section 5.9.2 . each of the temperature limits can be configured to act as inputs to the critical / thermal shutdown independent of the hardware shutdown operation. the analog portion of the critical/thermal shutdown function monitors a spec ific remote temperature channel (configured with the shdn_sel pin). this measured temperature is then compared with the trip_set point. this trip_set point is created by the system designer with a simple resistor and is discussed in detail in section 5.9.1 . 5.9.1 trip_set pin the EMC2112?s trip_set pin is an analog input to the critical/thermal shutdown block which sets the thermal shutdown temperature. the system desi gner creates a voltage level at the input through a simple resistor connected to gnd as shown in figure 5.1 . the value of this resistor is used to create an input voltage on the trip_set pin which is tr anslated into a temperature ranging from 60c to 122c enumerated in ta b l e 5 . 2 . figure 5.4 EMC2112 critical/the rmal shutdown block diagram v trip is the trip_set voltage [1] t min is the minimum temperature based on the range sys_shdn trip_set external diode 1 or external diode 2 critical shutdown logic smbus traffic sw_shdn configuration register vref shdn_sel pin decode register enabled sensor external diode 1 / 2 switch voltage conversion temperature conversion temperature conversion and limit registers register enabled sensor register enabled sensor v trip t trip t min ? 80 ---------------------------------- =
rpm-based linear fan controller with hardware thermal shutdown datasheet revision 0.88 (11-20-09) 28 smsc EMC2112 datasheet table 5.2 trip_set resistor setting t trip (c rset (1%) t trip (c) rset (1%) 60 0.0 92 1240 61 28.7 93 1330 62 48.7 94 1400 63 69.8 95 1500 64 90.9 96 1580 65 113 97 1690 66 137 98 1820 67 158 99 1960 68 182 100 2050 69 210 101 2210 70 237 102 2370 71 261 103 2550 72 294 104 2740 73 324 105 2940 74 348 106 3160 75 383 107 3480 76 412 108 3740 77 453 109 4120 78 487 110 4530 79 523 111 4990 80 562 112 5490 81 604 113 6040 82 649 114 6810 83 698 115 7870 84 750 116 9090 85 787 117 10700 86 845 118 12700 87 909 119 15800 88 953 120 20500
rpm-based linear fan controller with hardware thermal shutdown datasheet smsc EMC2112 29 revision 0.88 (11-20-09) datasheet 5.9.2 shdn_sel pin the EMC2112 has one ?strappable? input (shdn_sel) allowing for configuration of the hardware critical/thermal shutdown. this pin has 3 possi ble states and is monitored and decoded by the EMC2112 at power-up. the three possible states are 0 (tied to gnd), 1 (tied to 3.3v) or high-z (open). the states of this pin determine which remote te mperature channel and conf iguration is used by the critical/thermal shutdown function. the different configurations of shdn_sel pin are described in table 5.3 a channel that is configured via the shdn_sel pi n for the critical/thermal shutdown is locked and none of the configuration registers associated wit h it can be updated via the smbus. the other two temperature channels, how ever, are still configur able via the smbus. 5.9.3 internal hw_shdn signal the hw_shdn output from the critical/thermal shutdown monitor is a logical indicator of the temperature state of the chosen external diode channel. hw_shdn is an internal signal routed as an input to the thermal / critical shutdown logic. the hw_shdn output is set to logic ?1? when t he indicated temperature exceeds the temperature threshold (t p ) established by the trip_set input pin (as shown in figure 5.5 ) for a number of consecutive measurements defined by the fault queue. if the hw_shdn output is asserted and the temperature drops below t p , then it will be set to a logic ?0? state. 89 1020 121 29400 90 1100 122 49900 91 1150 60 open table 5.3 shdn_sel pin configuration shdn_sel function name critical/thermal shutdown details ?0? intel transistor mode (substrate pnp) the external diode 1 channel is configured with beta compensation enabled and resistance error correction enabled (with automatic detection). this mode is ideal for monitoring a substrate transistor such as an intel cpu thermal diode. high-z (open) amd cpu / diode mode the external diode 1 channel is configured with beta compensation disabled and resistance error correction disabled. this mode is ideal for monitoring an amd processor diode or a 2n3904 diode. ?1? external diode 2 diode mode the external diode 2 channel is linked to the hardware set thermal / critical shutdown circuitry and configured with beta compensation enabled (with automatic detection) and rec enabled. table 5.2 trip_set resistor setting (continued) t trip (c rset (1%) t trip (c) rset (1%)
rpm-based linear fan controller with hardware thermal shutdown datasheet revision 0.88 (11-20-09) 30 smsc EMC2112 datasheet 5.10 5v reset controller the EMC2112 also provides a ?power-good? reset c ontroller for the system?s 5v supply rail. the reset controller will set the reset pin to a logic ?0? after power-up and set the reset pin to a logic ?1? 220ms after the vdd_5v supply rises above its threshold voltage (see table 3.2 ). if the vdd_5v supply drops below the reset threshold, the reset pin will be set to ?0? immediately. 5.11 temperature monitoring the EMC2112 can monitor the temperature of up to three (3) externally connected diodes as well as the internal or ambient temperature. each channel is configured with the following features enabled or disabled based on user settings and system requirements. figure 5.5 hw_shdn operation figure 5.6 5v reset controller timing tp temperature hw_shdn not defined temperature exceeds tp temperature drops to tp or below measurements end after 4 th measurement, hw_shdn set vdd_5v reset threshold (4.4v) reset threshold - hysteresis (4.3v) reset# 220ms
rpm-based linear fan controller with hardware thermal shutdown datasheet smsc EMC2112 31 revision 0.88 (11-20-09) datasheet 5.11.1 dynamic averaging the EMC2112 supports dynamic averaging. when en abled, this feature chang es the conversion time for all external diode channels based on the select ed conversion rate. this essentially increases the averaging factor as shown in table 5.4 . the benefits of dynamic averaging are improved noise rejection due to the longer integration time as we ll as less random variation on the temperature measurement. 5.11.2 resistance error correction the EMC2112 includes active resistance error corre ction to remove the effect of up to 100 ohms of series resistance. without this aut omatic feature, voltage developed across the parasitic resistance in the remote diode path causes the temperature to read higher than the true temperature is. the error induced by parasitic resistance is approximately +0 .7c per ohm. sources of parasitic resistance include bulk resistance in the remote temperature transistor junctions, series resistance in the cpu, and resistance in the printed circuit board traces and package leads. resistance error correction in the EMC2112 eliminates the need to characterize and compensate for parasitic resistance in the remote diode path. 5.11.3 beta compensation the forward current gain, or beta, of a transistor is not constant as emitter currents change. this beta variation causes the measured v be (which is related to the collector current which, in turn, is related to beta) to shift in a way that is not predicted by the ratio of emitter currents being forced into the device. this shift cause an error in the temperature measurement. compensating for this error is also known as implementing the bjt or transis tor model for temperature measurement. for discrete transistors configured with the collect or and base shorted together, the beta is generally sufficiently high such that the percent change in beta variation is very small. for example, a 10% variation in beta for two forced emitter currents with a transistor whose ideal beta is 50 would contribute approximately 0.25c error at 100c. however for s ubstrate transistors where the base-emitter junction is used for temperature measurement and the collector is tied to the substrate, the proportional beta variation will cause large error. for example, a 10% variation in beta for two forced emitter currents with a transistor whose ideal beta is 0.5 would contribute approximately 8.25c error at 100c. the beta compensation circuitry in the EMC2112 correct s for this beta variation to eliminate any error which would normally be induced. this beta com pensation circuitry automatic ally detects the type of diode connected and adjusts the beta settings accordingly. table 5.4 dynamic averaging behavior conversion rate averaging factor (relati ve to 11-bit conversion) for external diode channels dynamic averaging enabled dynamic averaging disabled 1 / sec 8x 1x 2 / sec 4x 1x 4 / sec 2x 1x 8 / sec 1x 1x
rpm-based linear fan controller with hardware thermal shutdown datasheet revision 0.88 (11-20-09) 32 smsc EMC2112 datasheet 5.11.4 digital averaging the external diode 1 channel support a 4x digital av eraging filter. every cycle, this filter updates the temperature data based an a runnin g average of the last 4 measured temperature values. the digital averaging reduces temperature flickering and increases temperature measurement stability. the digital averaging can be disabled by setting the dis_avg bit in the configuration 2 register (see section 6.10 ). 5.12 diode connections the diode connection for the external diode 1 and external diode 2 channels are determined at power-up based on the shdn_sel pin (see section 5.9.2 ). this channel can support a diode- connected transistor (such as a 2n3904) or a substr ate transistor (such as those found in an cpu or gpu) as shown in figure 5.7 . the external diode 3 channel is available when the external diode 2 channel is configured to operate is an anti-parallel diode pair. in this mode, both the external diode 2 and external diode 3 diodes must be connected in the anti-paralle l configuration as shown in figure 5.7 5.12.1 diode faults the EMC2112 actively detects an open and short condition on each measurement channel. when a diode fault is detected, the temperature data most si gnificant byte is forced to a value of 80h and the fault bit is set in the status register. figure 5.7 diode connections local ground to dp typical remote substrate transistor i.e. cpu substrate pnp typical remote discrete pnp transistor i.e. 2n3906 typical remote discrete npn transistor i.e. 2n3904 to dn to dp to dn to dp to dn to dp / dn to dn / dp anti-parallel diodes using discrete npn transistors diode 2 diode 3
rpm-based linear fan controller with hardware thermal shutdown datasheet smsc EMC2112 33 revision 0.88 (11-20-09) datasheet chapter 6 register set 6.1 register map the following registers are accessible through the smbu s interface. all register bits marked as ?-? will always read ?0?. a write to these bits will have no effect. table 6.1 EMC2112 register set addr r/w register name function default value lock page temperature registers 00h r internal temp reading high byte stores the integer data of the internal diode 00h no page 36 01h r internal temp reading low byte stores the fractional data of the internal diode 00h no page 36 02h r external diode 1 temp reading high byte stores the integer data of external diode 1 channel 00h no page 36 03h r external diode 1 temp reading low byte stores the fractional data of external diode 1 00h no page 36 04h r external diode 2 temp reading high byte stores the integer data of external diode 2 channel 00h no page 36 05h r external diode 2 temp reading low byte stores the fractional data of external diode 2 00h no page 36 06h r external diode 3 temp reading high byte stores the integer data of external diode 3 channel 00h no page 36 07h r external diode 3 temp reading low byte stores the fractional data of external diode 3 00h no page 36 0ah r critical/thermal shutdown temperature stores the calculated critical/thermal shutdown temperature high limit derived from the voltage on trip_set 7fh (+127c) no page 37 10h r trip set voltage stores the raw measured trip_set voltage input ffh no page 38 diode configuration 11h r/w external diode 1 ideality configures ideality factor settings for external diode 1 12h swl page 38 12h r/w external diode 2 ideality configures ideality factor settings for external diode 2 12h swl page 38 13h r/w external diode 3 ideality configures ideality factor settings for external diode 3 12h swl page 38
rpm-based linear fan controller with hardware thermal shutdown datasheet revision 0.88 (11-20-09) 34 smsc EMC2112 datasheet 14h r/w external diode 1 beta configuration configures the beta compensation settings for external diode 1 10h swl page 39 15h r/w external diode 2 beta configuration configures the beta compensation settings for external diode 2 10h swl page 39 17h r/w external diode rec configuration configures the resistance error correction functionality for all external diodes 07h swl page 41 19h r/w external diode 1 tc r i t l i m i t stores the critical temperature limit for the external diode 1 64h (100c) write lock page 41 1ah r/w external diode 2 tc r i t l i m i t stores the critical temperature limit for the external diode 2 64h (100c) write lock page 41 1bh r/w external diode 3 tc r i t l i m i t stores the critical temperature limit for the external diode 3 64h (100c) write lock page 41 1dh r/w internal diode tc r i t l i m i t stores the critical temperature limit for the internal diode 64h (100c) write lock page 41 configuration and control 1fh r-c tcrit limit status stores the status bits for all temperature channel tcrit limits 00h no page 45 20h r/w configuration configures the thermal / critical shutdown masking options and software lock 00h swl page 42 21h r/w configuration 2 controls the conversion rate for monitoring of all channels 0eh swl page 43 23h r-c interrupt status stores the status bits for temperature channels 00h no page 44 24h r-c high limit status stores the status bits for all temperature channel high limits 00h no page 45 26h r-c diode fault stores the status bits for all temperature channel diode faults 00h no page 45 27h r-c fan status stores the status bits for the rpm- based fan speed control algorithm 00h no page 46 28h r/w interrupt enable register controls the masking of interrupts on all temperature channels 00h no page 46 29h r/w fan interrupt enable register controls the masking of interrupts on all fan related channels 00h no page 47 temperature limit registers 30h r/w external diode 1 temp high limit high limit for external diode 1 55h (+85c) swl page 47 31h r/w external diode 2 temp high limit high limit for external diode 2 55h (+85c) swl page 47 table 6.1 EMC2112 regi ster set (continued) addr r/w register name function default value lock page
rpm-based linear fan controller with hardware thermal shutdown datasheet smsc EMC2112 35 revision 0.88 (11-20-09) datasheet 32h r/w external diode 3 temp high limit high limit for external diode 3 55h (+85c) swl page 47 34h r/w internal diode high limit high limit for internal diode 55h (85c) swl page 47 fan control registers 40h r/w fan setting always displays the most recent fan driver input setting for the fan. if the rpm-based fan speed control algorithm is disabled, allows direct user control of the fan driver. 00h no page 48 42h r/w fan configuration 1 sets configuration values for the rpm- based fan speed control algorithm for the fan driver 2bh no page 48 43h r/w fan configuration 2 sets additional configuration values for the fan driver 28h swl page 50 45h r/w gain holds the gain terms used by the rpm- based fan speed control algorithm for the fan driver 2ah swl page 51 46h r/w fan spin up configuration sets the configuration values for spin up routine of the fan driver 19h swl page 52 47h r/w fan step sets the maximum change per update for the fan driver 10h swl page 53 48h r/w fan minimum drive sets the minimum drive value for the fan driver 66h (40%) swl page 54 49h r/w fan valid tach count holds the minimum tachometer reading that indicates the fan is spinning properly f5h swl page 54 4ah r/w fan drive fail band low byte stores the number of tach counts used to determine how the actual fan speed must match the target fan speed at full scale drive 00h swl page 55 4bh r/w fan drive fail band high byte 00h swl 4ch r/w tach target low byte holds the target tachometer reading low byte the fan f8h no page 55 4dh r/w tach target high byte holds the target tachometer reading high byte for the fan ffh no page 55 4eh r tach reading high byte holds the tachometer reading high byte for the fan ffh no page 55 4fh r tach reading low byte holds the tachometer reading low byte for the fan f8h no page 55 lock register ef r/w software lock locks all swl registers 00h swl page 56 table 6.1 EMC2112 regi ster set (continued) addr r/w register name function default value lock page
rpm-based linear fan controller with hardware thermal shutdown datasheet revision 0.88 (11-20-09) 36 smsc EMC2112 datasheet during power-on-reset (por), the default values are stored in the registers. a por is initiated when power is first applied to the part and the voltage on the vdd_3v supply surpasses the por level as specified in the electrical charac teristics. any reads to undefined registers will return 00h. writes to undefined registers will not have an effect. 6.1.1 lock entries the lock column describes the locking mechanism, if any, used for individual registers. all swl registers are software locked and therefore made read-only when the lock bit is set. 6.2 temperature data registers revision registers fch r product features stores information about which pin controlled product features are set 00h no page 57 fdh r product id stores the unique product id 15h no page 57 feh r manufacturer id stores the manufacturer id 5dh no page 58 ffh r revision revision 01h no page 58 table 6.2 temperature data registers addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default 00h r internal diode high byte sign 64 32 16 8 4 2 1 00h 01h r internal diode low byte 0.5 0.25 0.125 - - - - - 00h 02h r external diode 1 high byte sign 64 32 16 8 4 2 1 00h 03h r external diode 1 low byte 0.5 0.25 0.125 - - - - - 00h 04h r external diode 2 high byte sign 64 32 16 8 4 2 1 00h 05h r external diode 2 low byte 0.5 0.25 0.125 - - - - - 00h 06h r external diode 3 high byte sign 64 32 16 8 4 2 1 00h 07h r external diode 3 low byte 0.5 0.25 0.125 - - - - - 00h table 6.1 EMC2112 regi ster set (continued) addr r/w register name function default value lock page
rpm-based linear fan controller with hardware thermal shutdown datasheet smsc EMC2112 37 revision 0.88 (11-20-09) datasheet the temperature measurem ent range is from -64c to +128c. the data format is a signed two?s complement number as shown in table 6.3 . application note: when the external diode 3 channel is not enabled, the data bytes will read 00h. 6.3 critical/thermal shut down temperature registers the critical/thermal shutdown temper ature register is a read-only r egister that stores the voltage programmable threshold temperature used in the thermal / critical shutdown circuitry. the contents of the register reflect the calc ulated temperature based on the trip_set voltage. this register is updated at the end of every monitoring cycle based on the current value of the trip_set voltage. the data format is shown in ta b l e 6 . 5 . table 6.3 temperature data format temperature (c) binary hex (as read by registers) diode fault 1000_0000_000b 80_00h -63.875 1100_0000_001b c0_20h -63 1100_0001_000b c1_00h -1 1111_1111_000b ff_00h -0.125 1111_1111_111b ff_e0h 0 0000_0000_000b 00_00h 0.125 0000_0000_001b 00_20h 1 0000_0001_000b 01_00h 63 0011_1111_000b 3f_00h 64 0100_0000_000b 40_00h 65 0100_0001_000b 41_00h 127 0111_1111_000b 7f_00h 127.875 0111_1111_111b 7f_e0h table 6.4 critical/thermal shutdown temperature registers addrr/wregister b7b6b5b4b3b2b1b0default 0ah r critical/thermal shutdown temperature - 643216 8 4 2 1 7fh (+127c) table 6.5 critical / thermal shutdown data format temperature (c) binary hex 0 0000_0000b 00h 1 0000_0001b 01h
rpm-based linear fan controller with hardware thermal shutdown datasheet revision 0.88 (11-20-09) 38 smsc EMC2112 datasheet 6.4 tripset voltage register the tripset voltage register stores the measured voltage on the trip_set pin that is used to calculate the critical / thermal s hutdown temperature. each bit wei ght represents mv of resolution so that the final voltage can be determined by adding the appropriately set bits together. 6.5 ideality factor registers these registers store the ideality factors t hat are applied to the external diodes. beta compensation and resistance error correction automatically correct for most diode ideality errors, therefore it is not recommended that th ese settings be updated without consulting smsc. for cpu substrate transistors that require the bjt transistor model, the ideality factor behaves slightly differently than for discrete di ode-connected transistors. refer to ta b l e 6 . 9 when using a cpu substrate transistor. only the lower three bits can be written. writing to any other bit will be ignored. the ideality factor regist ers are software locked. 63 0011_1111b 3fh 64 0100_0000b 40h 65 0100_0001b 41h 127 0111_1111b 7fh table 6.6 tripset voltage register addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default 10h r tripset voltage 400 200 100 50 25 12.5 6.25 3.125 ffh table 6.7 ideality factor registers addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default 11h r/w external diode 1 ideality 00010b2b1b012h 12h r/w external diode 2 ideality 00010b2b1b012h 13h r/w external diode 3 ideality 00010b2b1b012h table 6.5 critical / thermal shutdown data format (continued) temperature (c) binary hex
rpm-based linear fan controller with hardware thermal shutdown datasheet smsc EMC2112 39 revision 0.88 (11-20-09) datasheet application note: when measuring a 65nm intel cpus, the idealit y setting should be the default 12h. when measuring 45nm intel cpus, t he ideality setting should be 15h. 6.6 beta configuration registers table 6.8 ideality factor look-up table setting factor 10h 1.0053 11h 1.0066 12h 1.0080 13h 1.0093 14h 1.0106 15h 1.0119 16h 1.0133 17h 1.0146 table 6.9 substrate diode ideality factor look-up table (bjt model) setting factor 10h 0.9973 11h 0.9986 12h 1.0000 13h 1.0013 14h 1.0026 15h 1.0039 16h 1.0053 17h 1.0066 table 6.10 beta configuration registers addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default 14h r/w external diode 1 beta configuration --- auto 1 beta1[3:0] 10h 15h r/w external diode 2 beta configuration --- auto 2 beta2[3:0] 10h
rpm-based linear fan controller with hardware thermal shutdown datasheet revision 0.88 (11-20-09) 40 smsc EMC2112 datasheet the beta configuration registers control advanc ed temperature measurem ent features for each external diode channel. the beta configuration re gisters are software locked. the external diode 1 beta configuration register is hardware locked if the external diode 1 channel is linked to the hardware critical / thermal shutdown circuitry. likewise, th e external diode 2 beta configuration register is hardware locked if the external diode 2 is linked to the critical / thermal shutdown circuitry - see section 5.9.2 . bit 4 - auto - enables the automatic beta detection algorithm. ? ?0? - the automatic beta detection algorithm is disabled. the betax[3:0] bit settings will be used to control the beta compensation circuitry. ? ?1? (default) - the automatic beta detection algo rithm is enabled. the circuitry will automatically detect the transistor type and beta values and configure the betax[3:0] bits for optimal performance. bits 3 - 0 - betax[3:0] - hold a value that corresponds to a range of betas t hat the beta compensation circuitry can compensate for. these four bits will always show the current beta setting used by the circuitry. if the auto bit is set (default), t hen these bits may updated by the device with every temperature conversion. if the auto bit is not set, then the value of these bits is used to drive the beta compensation circuitry. in this case, these bits should be set with a va lue corresponding to the lowest expected value of beta for the pnp transi stor being used as a temperature sensing device. see table 6.11 for supported beta ranges. a value of 1111b indicates that the beta compensation circuitry is disabled. in this condition, the diode channels will function with default current levels and will not automatically adjust for beta variation. th is mode is used when measuring a discrete 2n3904 transistor or amd thermal diode. all of the beta configuration registers are software locked. table 6.11 beta compensation auto betax[3:0] minimum beta 3210 00000 0.050 00001 0.066 00010 0.087 00011 0.114 00100 0.150 00101 0.197 00110 0.260 00111 0.342 01000 0.449 01001 0.591 01010 0.778 01011 1.024 01100 1.348 01101 1.773
rpm-based linear fan controller with hardware thermal shutdown datasheet smsc EMC2112 41 revision 0.88 (11-20-09) datasheet 6.7 rec configuration register the rec configuration register determines whether resistance error correction is used for each external diode channel. the rec confi guration register is software locked. if either the external diode 1 channel or external diode 2 channel is selected by the shdn_sel pin to be the hardware shutdown input channel (see table 5.3 ), then the corresponding recx bit will be locked. writing to the bit will have no affect and re ading from it will always report the current setting. bit 2 - rec3 - controls the resistive error correction functionality of external diode 3 ? ?0? - the rec functionality for external diode 3 is disabled ? ?1? (default) - the rec functionalit y for external diode 3 is enabled. bit 1 - rec2 - controls the resistive error correction functionality of external diode 2 ? ?0? - the rec functionality for external diode 2 is disabled ? ?1? (default) - the rec functionalit y for external diode 2 is enabled. bit 0 - rec1 - controls the resistive error correction functionality of external diode 1 ? ?0? - the rec functionality for external diode 1 is disabled ? ?1? (default) - the rec functionalit y for external diode 1 is enabled. 6.8 critical temper ature limit registers 01110 2.333 01111 disabled 1 x x x x automatically detected table 6.12 rec configuration register address r/w register b7 b6 b5 b4 b3 b2 b1 b0 default 17h r/w rec configuration - - - - - rec3 rec2 rec1 07h table 6.13 tcrit limit registers addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default 19h r/w once external diode 1 tcrit limit sign 64 32 16 8 4 2 1 64h (+100c) 1ah r/w once external diode 2 tcrit limit sign 64 32 16 8 4 2 1 64h (+100c) table 6.11 beta compensation (continued) auto betax[3:0] minimum beta 3210
rpm-based linear fan controller with hardware thermal shutdown datasheet revision 0.88 (11-20-09) 42 smsc EMC2112 datasheet the critical temperature limit regi sters store the critical temperatur e limit. at power up, none of the respective channels are linked to hardware set thermal/critical shutdown circuitry. whenever one of the registers is updated, two things occu r. first, the register is locked so that it cannot be updated again without a power on reset. second, t he respective temperature channel is linked to the sys_shdn pin and the hardware set thermal/critical shutdown circuitry. at this point, if the measured temperature channel exceeds the critical limit, the sys_shdn pin will be asserted, the appropriate bit set in the tcrit status register, and the tcrit bit in the interrupt status register will be set. 6.9 configuration register the configuration register controls the basic fu nctionality of the EMC2112. the bits are described below. the configuration register is software locked. bit 7 - mask - blocks the alert pin from being asserted. ? ?0? (default) - the alert pin is unmasked. if any bit in either status register is set, the alert pins will be asserted (unless individually masked via the mask register) ? ?1? - the alert pin is masked and will not be asserted. bit 6 - wd_en - enables the watchdog timer to operate in continuous mode (see section 5.6.2 ). ? ?0? (default) - the watchdog timer does not operate continuously. it will function upon power up and at no other time. ? ?1? - the watchdog timer operates continuously as described in section 5.6 . bit 2 - dr_ext_clk - enables the internal tachometer clock to be driven out on the clk pin so that multiple devices can be synced to the same source. ? ?0? (default) - the clk pin acts as a clock input. ? ?1? - the clk pin acts as a clock output and is a push-pull driver. bit 1 - use_ext_clk - enables the EMC2112 to use a clock present on the clk pin as the tachometer clock. if the dr_ext_clk bit is set, then this bit is ignored and the device will use the internal oscillator. ? ?0? (default) - the EMC2112 will use its internal oscillator for all tachometer measurements. ? ?1? - the EMC2112 will use the oscillator pr esented on the clk pin for all tachometer measurements. 1bh r/w once external diode 2 tcrit limit sign 64 32 16 8 4 2 1 64h (+100c) 1dh r/w once internal diode tcrit limit sign 64 32 16 8 4 2 1 64h (+100c) table 6.14 configuration register addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default 20h r/w configuration mask wd_ en --- dr_ ext_ clk use_ ext_ clk apd 00h table 6.13 tcrit limit registers (continued) addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default
rpm-based linear fan controller with hardware thermal shutdown datasheet smsc EMC2112 43 revision 0.88 (11-20-09) datasheet bit 0 - apd - enables the external diode 3 channel. ? ?0? (default) - the external diode 3 channel is not enabled. ? ?1? - the external diode 3 channel is enabled as an anti-parallel diode connected to dp2 / dn2 pins. 6.10 configuration 2 register the configuration 2 register cont rols conversion rate of the tem perature monitoring as well as the fault queue. this register is software locked. bit 6 - dis_dyn - disables the dynamic averaging feature. ? ?0? (default) - the dynamic averagin g function is enabled. the conversion time for all external diode temperature channels is scaled based on the chosen conversion rate to maximize accuracy and immunity to random temper ature measurement variation. ? ?1? - the dynamic averaging function is disabled. the conversion time for all temperature channels is fixed regardless of the chosen conversion rate. bit 5 - dis_to - disables the smbus time out function for the smbus client (if enabled). ? ?0? (default) - the smbus timeout and idle functi onality are enabled. the smbus interface will time out if the clock line is held low for longer than 30ms . likewise, it will reset if both the data and clock lines are held high for longer than 150us. ? ?1? - the smbus timeout and idle functionality are disabled. the smbus interface will not time out if the clock line is held low. likewise, it will not reset if both the data and clock lines are held high for longer than 150us. this is used for i 2 c compliance. bit 4 - dis_avg - disables digital averaging of the external diode 1 channel. ? ?0? (default) - the external diode 1 channel has di gital averaging enabled. the temperature data is the average of the previous four measurements. ? ?1? - the external diode 1 channel has digital averaging disabled. the temperature data is the last measured data. bits 3-2 - queue[1:0] - determines the number of consecutive out of limit conditions that are necessary to trigger an interrupt. each measurem ent channel has a separate fault queue associated with the high limit and diode fault c ondition except the internal diode. the critical / thermal shutdown temperature has a separate fault queue that applies to the selected hardware shutdown channel (see section 5.9 ) when compared against the threshold set by the trip_set pin. application note: if the fault queue for any channel is currently active (i.e. an out of limit condition has been detected and caused the fault queu e to increment) then changing the settings will not take effect until the fault queue is zeroed. this occurs by the alert pin asserting or the out of limit condition being removed. table 6.15 configuration 2 register addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default 21h r/w config 2 - dis_ dyn dis_ to dis_ avg queue[1:0] conv[1:0] 0eh
rpm-based linear fan controller with hardware thermal shutdown datasheet revision 0.88 (11-20-09) 44 smsc EMC2112 datasheet bit 1 - 0 - conv[1:0] - determines the conversion ra te of the temperature monitoring. this conversion rate does not affect the fan driver. the supply cu rrent from vdd_3v is nominally dependent upon the conversion rate and the average current will in crease as the conversion rate increases. 6.11 interrupt status register the interrupt status register reports the operating co ndition of the EMC2112. if any of the bits are set to a logic ?1? (o ther than reset and tsd), the alert pin will be asserted low if the corresponding channel is enabled. if there are no set status bits, the alert pin will be released. the bits that cause the alert pin to be asserted can be masked based on the channel they are associated with unless stated otherwise. bit 7 - reset - this bit is set to ?1? if the rese t generator (see section 5.10 ) has tripped, meaning that the vdd_5v voltage level is less than its normal operating level (and the reset pin is at a logic ?0? state). this bit is cleared wh en the reset output changes states to a logic ?1?. this bit will not cause the alert pin to be asserted. table 6.16 fault queue queue[1:0] number of consecutive out of limit conditions 10 0 0 1 (disabled) 01 2 10 3 1 1 4 (default) table 6.17 conversion rate conv[1:0] conversion rate temperature over sampling from 11 bits 1 0 dyn_dis = ?0? dyn_dis = ?1? 0 0 1 / sec x8 x1 0 1 2 / sec x4 x1 1 0 4 / sec (default) x2 x1 1 1 8 / sec x1 x1 table 6.18 interrupt status register addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default 23h r-c interrupt status register reset tsd tcrit - fan high - fault 00h
rpm-based linear fan controller with hardware thermal shutdown datasheet smsc EMC2112 45 revision 0.88 (11-20-09) datasheet bit 6 - tsd - this bit is set to ?1? if the internal thermal shutdown (tsd) circuit trips indicating that the die temperature has exceeded its threshold. when this bit is set, it will not cause the alert pin to be asserted however will coincide with the sys_shdn pin being asserted. this bit is cleared when the register is read and the error condition has been removed. bit 5 - tcrit - this bit is set to ?1? whenever the any bit in the tcrit status register is set. this bit is automatically cleared when the tcri t status register is cleared. bit 3 - fan - this bit is set to ?1? if any bit in the fan status register is set. this bit is automatically cleared when the fan status register is read and the bits are cleared. bit 2 - high - this bit is set to ?1? if any bit in the high status register is set. this bit is automatically cleared when the high status register is read and the bits are cleared. bit 0 - fault - this bit is set to ?1? if any bit in t he diode fault register is set. this bit is automatically cleared when the diode fault register is read and the bits are cleared. 6.12 error status registers the error status registers report the specific error condition for all measurement channels with limits. if any bit is set in the high, low, or diode fault st atus register, the corresponding high, low, or fault bit is set in the interrupt status register. reading the interrupt status register does not clea r the error status bit. reading from any error status register that has bits set will clear the register and the corresponding bit in the interrupt status register if the error condition has been removed. if the error condition is pe rsistent, reading the error status registers will have no affect. 6.12.1 tcrit status register the tcrit status register stores the event that c aused the sys_shdn pin to be asserted. each of the temperature channels must be associated with the sys_shdn pin before the corresponding status bit can be set (see section 6.8 ). once the sys_shdn pin is asserted, it will be released when the temperature drops below the threshold level however the individual status bit will not be cleared until read. bit 7 - hws - this bit is set if the hardware set temperature channel meets or exceeds the temperature threshold determined by the trip_set voltage. table 6.19 error status register addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default 1fh r-c tcrit status hws - - - ext3_ crit ext2_ crit ext1_ crit int_ crit 00h 24h r-c high status - - - - ext3_ hi ext2_ hi ext1_ hi int_ hi 00h 26h r-c diode fault - - - - ext3_ flt ext2_ flt ext1_ flt - 00h
rpm-based linear fan controller with hardware thermal shutdown datasheet revision 0.88 (11-20-09) 46 smsc EMC2112 datasheet 6.13 fan status register the fan status register contains the status bits associated with each fan driver. this register is cleared when read if the erro r condition has been removed. bit 7 - watch - this bit is asserted ?1? if the watchdog timer has expired (see section 5.6 ). bit 5 - drive_fail - indicates that the rpm-based fan speed control algorithm cannot drive the fan to the desired target setting at maximum drive. this bit can be masked from asserting the alert pin. ? ?0? - the rpm-based fan speed control algorithm can drive the fan to the desired target setting. ? ?1? - the rpm-based fan speed control algorithm cannot drive the fan to the desired target setting at maximum drive. bit 4- fan_short - this bit is asserted ?1? if the high side fan driver detects an over current condition that lasts for longer than 2 seconds. bit 1- fan_spin- this bit is asserted ?1? if t he spin up routine for the fan cannot detect a valid tachometer reading within its maximum time window. this bit can be masked from asserting the alert pin. bit 0 - fan_stall - this bit is asserted ?1? if the tachometer measurement on the fan detects a stalled fan. this bit can be masked from asserting the alert pin. 6.14 interrupt enable register the interrupt enable register controls the masking for each temperature channel. when a channel is masked, it will not cause the alert pin to be asserted when an error condition is detected. bit 3 - ext3_int_en - allows the external diode 3 channel to assert the alert pin. this bit can only be set if the apd bit is set. ? ?0? (default) - the alert pin will not be asserted for any error condition associated with external diode 3 channel. ? ?1? - the alert pin will be asserted for an error condition associated with external diode 3 channel. bit 2 - ext2_int_en - allows the external diode 2 channel to assert the alert pin. ? ?0? (default) - the alert pin will not be asserted for any error condition associated with external diode 2 channel. ? ?1? - the alert pin will be asserted for an error condition associated with external diode 2 channel. table 6.20 fan status register addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default 27h r-c fan status register watch - drive_ fail fan_ short -- fan_ spin fan_ stall 00h table 6.21 interrupt enable register addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default 28 r/w interrupt enable -- -- ext3_ int_en ext2_ int_en ext1_ int_en int_ int_en 00h
rpm-based linear fan controller with hardware thermal shutdown datasheet smsc EMC2112 47 revision 0.88 (11-20-09) datasheet bit 1 - ext1_int_en - allows the external diode 1 channel to assert the alert pin. ? ?0? (default) - the alert pin will not be asserted for any error condition associated with external diode 1 channel. ? ?1? - the alert pin will be asserted for an error condition associated with external diode 1 channel. bit 0 - int_int_en - allows the internal diode channel to assert the alert pin. ? ?0? (default) - the alert pin will not be asserted for any error condition associated with the internal diode. ? ?1? - the alert pin will be asserted for an error condition associated with the internal diode. 6.15 fan interrupt enable register the fan interrupt enable controls the masking for each fan channel. when a channel is enabled, it will cause the alert pin to be asserted when an error condition is detected. bit 1 - spin_int_en - allows the fan_spin bit to assert the alert pin. ? ?0? (default) - the fan_spin bit will not assert the alert pin though it will st ill update the status register normally. ? ?1? - the fan_spin bit will assert the alert pin. bit 0 - stall_int_en - allows the fan_stall bit or drive_fail bit to assert the alert pin. ? ?0? (default) - the fan_stall bit or drive_fail bit will not assert the alert pin though will still update the status register normally. ? ?1? - the fan_stall or drive_fail bit will assert the alert pin if set. 6.16 limit registers table 6.22 fan interrupt enable register addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default 29h r/w fan interrupt enable ----- - spin_ int_en stall_ int_en 00h table 6.23 limit registers addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default 30h r/w external diode 1 high limit sign 64 32 16 8 4 2 1 55h (+85c) 31h r/w external diode 2 high limit sign 64 32 16 8 4 2 1 55h (+85c) 32h r/w external diode 3 high limit sign 64 32 16 8 4 2 1 55h (+85c) 34h r/w internal diode high limit sign 64 32 16 8 4 2 1 55h (+85c)
rpm-based linear fan controller with hardware thermal shutdown datasheet revision 0.88 (11-20-09) 48 smsc EMC2112 datasheet the EMC2112 contains high limits for all te mperature channels and vo ltage channels. if any measurement meets or exceeds the high limit then t he appropriate status bit is set and the alert pin is asserted (if enabled). all limit registers are software locked. 6.17 fan setting register the fan setting register always displays the current setting of the fan driver. reading from the register will report the current fan speed setting of the fan driver regardless of the operating mode. therefore it is possible that read ing from this register will not report data that was previously written into this register. while the rpm-based fan speed control algorithm is ac tive, then the register is read only. writing to the register will have no affect and the data will not be stored. if the rpm-based fan control algorithm is disabled, then the register will be set with the previous value that was used. the register is read / write an d writing to this register will affect the fan speed. the contents of the register repr esent the weighting of each bit in determining the final output voltage. the output drive for the high side fan driver output is given by equation [2] . 6.18 fan configuration 1 register the fan configuration 1 register controls the ge neral operation of the rpm-based fan speed control algorithm used for the fan 1 driver. bit 7 - en_algo - enables the rpm-based fan speed control algorithm. ? ?0? - (default) the control circuitry is disabled and the fan driver output is determined by the fan driver setting register. ? ?1? - the control circuitry is enabled and the fa n driver output will be automatically updated to maintain the programmed fan speed as indicated by the tach target register. bits 6- 5 - range[1:0] - adjusts the range of re ported and programmed tac hometer reading values. the range bits determine the weighting of all tach values (including the valid tach count, tach target, and tach reading) as shown in ta b l e 6 . 2 6 . table 6.24 fan setting register addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default 40h r/w fan setting 128 64 32 16 8 4 2 1 00h [2] table 6.25 fan configuration 1 register addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default 42h r/w fan configuration 1 en_ algo range[1:0] edges[1:0] update[2:0] 2bh drive value 255 -------------------- - ?? ?? vdd _5v =
rpm-based linear fan controller with hardware thermal shutdown datasheet smsc EMC2112 49 revision 0.88 (11-20-09) datasheet bits 4-3 - edges[1:0] - determine s the minimum number of edges t hat must be detected on the tach signal to determine a single rotation. a typical fan measured 5 edges (for a 2-pole fan). for more accurate tachometer measurement, the minimu m number of edges measured may be increased. increasing the number of edges m easured with respect to the number of poles of the fan will cause the tach reading registers to indicate a fan speed that is higher or lowe r than the actual speed. in order for the fsc algorithm to operate correctly, the tach target must be updated by the user to accommodate this shift. the effective tach multiplier shown in ta b l e 6 . 2 7 is used as a direct multiplier term that is applied to the actual rpm to achieve the reported rpm. it should only be applied if the number of edges measured does not match the numbe r of edges expected based on the number of poles of the fan (which is fixed for any given fan). contact smsc for recommended settings when us ing fans with more or less than 2 poles. bit 2-0 - update - determines the base time be tween fan driver updates. the update time, along with the fan step register, is used to control the ra mp rate of the drive response to provide a cleaner transition of the actual fan operation as the de sired fan speed changes. the update time is set as shown in ta b l e 6 . 2 8 . table 6.26 range decode range[1:0] reported minimum rpm tach count multiplier 10 005001 0 1 1000 (default) 2 1 0 2000 4 1 1 4000 8 table 6.27 minimum edges for fan rotation edges[1:0] minimum tach edges number of fan poles effective tach multiplier (based on 2 pole fans) 10 0 0 3 1 pole 0.5 0 1 5 2 poles (default) 1 1 0 7 3 poles 1.5 1 1 9 4 poles 2 table 6.28 update time update[2:0] update time 21 0 00 0 100ms 00 1 200ms 01 0 300ms
rpm-based linear fan controller with hardware thermal shutdown datasheet revision 0.88 (11-20-09) 50 smsc EMC2112 datasheet 6.19 fan configuration 2 register the fan configuration 2 register controls the tac hometer measurement and ad vanced features of the rpm-based fan speed control algorithm. bit 7 - temp_rr - overrides max step controls for the fsc algorithm wh en any temperature exceeds its respective high limit. ? ?0? (default) - all ramp rate contro l circuitry works at all times for the fsc algorithm or as determined by the en_rrc bit for manual mode. ? ?1? - if any measured temperatur e or the pwm input duty cycle meets or exceeds its respective high limit, then the fan max step register settings are not used and the fsc algorithm acts as if the max step settings were at 3fh. the device will continue to operate in this way until all temperatures (and the pwm input duty cycle) have dropped below the respective high limit. bit 6 - en_rrc - enables ramp rate control when th e fan driver is operated in the direct setting mode. ? ?0? (default) - ramp rate control is disabled. when the fan driv er is operating in direct setting mode, the fan setting will instantly transitio n to the next programmed setting. ? ?1? - ramp rate control is enabled. when the fan driver is operating in direct setting mode, the fan drive setting will follow the ramp rate controls as determined by the fan step and update time settings. the maximum fan drive setting step is capped at the fan step setting and is updated based on the update time as given by table 6.28 . bit 5 - glitch_en - disables the low pass glitch filt er that removes high frequency noise injected on the tach pin. ? ?0? - the glitch filter is disabled. ? ?1? (default) - the glit ch filter is enabled. bits 4 - 3 - der_opt[1:0] - control some of the adv anced options that affect the derivative portion of the rpm-based fan speed control algorithm as shown in ta b l e 6 . 3 0 . 0 1 1 400ms (default) 10 0 500ms 10 1 800ms 1 1 0 1200ms 1 1 1 1600ms table 6.29 fan configuration 1 register addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default 43h r/w fan configuration 2 temp_ rr en_ rrc glitch_ en der_opt [1:0] err_rng[1:0] - 28h table 6.28 update time (continued) update[2:0] update time 21 0
rpm-based linear fan controller with hardware thermal shutdown datasheet smsc EMC2112 51 revision 0.88 (11-20-09) datasheet bit 2 - 1 - err_rng[1:0] - control some of the adv anced options that affect the error window. when the measured fan speed is within the programmed error window around the target speed, then the fan drive setting is not updated. the algorithm will continue to monitor the fan speed and calculate necessary drive setting changes based on t he error, however these changes are ignored. 6.20 gain register the gain register stores the gain terms used by th e proportional and integral portions of each of the rpm-based fan speed control algorithms. these gain terms are used as the kd, ki, and kp gain terms in a classic pid control solution. table 6.30 deri vative options der_opt[1:0] operation 10 0 0 no derivative options used 01 basic derivative. the derivative of the error from the current drive setting and the ta rget is added to the iterative fan drive register setting (in addition to proportional and integral terms) (default) 10 step derivative. the derivative of the error from the current drive setting and the ta rget is added to the iterative fan drive register setting and is not capped by the fan step register. this allows faster response times than the basic derivative. 11 both the basic derivative and the step derivative are used effectively causing the derivative term to have double the effect of the derivative term. table 6.31 error range options err_rng[1:0] operation 10 0 0 0 rpm (default) 0 1 50 rpm 1 0 100 rpm 1 1 200 rpm table 6.32 gain register addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default 45h r/w gain register - - gaind[ 1:0] gaini[1:0] gainp[1:0] 2ah
rpm-based linear fan controller with hardware thermal shutdown datasheet revision 0.88 (11-20-09) 52 smsc EMC2112 datasheet 6.21 fan spin up configuration register the fan spin up configuration register controls the settings of spin up routine. the fan spin up configuration register is software locked. bit 7 - 6 - drive_fail_cnt[1:0] - determines ho w many update cycles are used for the drive fail detection function as shown in ta b l e 6 . 3 5 . this circuitry determines whether the fan can be driven to the desired tach target. bit 5 - nokick - determines if the spin up routine will drive the fan to 100% duty cycle for 1/4 of the programmed spin up time before dr iving it at the programmed level. ? ?0? (default) - the spin up routine will drive the fa n driver to 100% for 1/4 of the programmed spin up time before re verting to the programmed spin level. ? ?1? - the spin up routine will not drive the fan driver to 100%. it will set the drive at the programmed spin level for the entire dur ation of the programmed spin up time. table 6.33 gain decode gaind or gainp or gaini [1:0] respective gain factor 10 00 1x 01 2x 1 0 4x (default) 11 8x table 6.34 fan spin up configuration register addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default 46h r/w fan spin up configuration drive_fail_ cnt [1:0] nok ick spin_lvl[2:0] spinup_ time[1:0] 19h table 6.35 drive_fail_cnt[1:0] bit decode drive_fail_cnt[1:0] number of update periods 10 0 0 disabled - the drive fail detection circuitry is disabled (default) 0 1 16 - the drive fail detection circuitry will count for 16 update periods 1 0 32 - the drive fail detection circuitry will count for 32 update periods 1 1 64 - the drive fail detection circuitry will count for 64 update periods
rpm-based linear fan controller with hardware thermal shutdown datasheet smsc EMC2112 53 revision 0.88 (11-20-09) datasheet bits 4 - 2 - spin_lvl[2:0] - determines the final dr ive level that is used by the spin up routine as shown in ta b l e 6 . 3 6 . bit 1 -0 - spinup_time[1:0] - determines the maximu m spin time that the spin up routine will run for (see section 5.2 ). if a valid tachometer measurement is not detected before the spin time has elapsed, then an interrupt will be generated. when the rpm-based fan speed control algorithm is active, the fan driver will attempt to re-start the fan immediately after the end of the last spin up attempt. the spin time is set as shown in ta b l e 6 . 3 7 . 6.22 fan max step register the fan max step register, along with the update time , controls the ramp rate of the fan driver response calculated by the rpm-based fan speed control algorithm. the value of the registers represents the maximum step size each fan driver will take between update times (see section 6.18 ). table 6.36 spin level spin_lvl[2:0] spin up drive level 210 0 0 0 30% 0 0 1 35% 0 1 0 40% 0 1 1 45% 1 0 0 50% 1 0 1 55% 1 1 0 60% (default) 1 1 1 65% table 6.37 spin time spinup_time[1:0] total spin up time 10 0 0 250 ms 0 1 500 ms (default) 1 0 1 sec 1 1 2 sec table 6.38 fan max step register addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default 47h r/w fan max step - - 32 16 8 4 2 1 10h
rpm-based linear fan controller with hardware thermal shutdown datasheet revision 0.88 (11-20-09) 54 smsc EMC2112 datasheet when the fsc algorithm is enabled, ramp rate cont rol is automatically us ed. when the fsc is not active, then ramp rate control can be ena bled by asserting the en_rrc bit (see section 6.19 ) application note: the update bits and fan step register se ttings operate independently of the rpm-based fan speed control algorithm and will always limit the fan drive setting. that is, if the programmed fan drive setting (either in dete rmined by the rpm-based fan speed control algorithm or by manual settings) exceeds the cu rrent fan drive setting by greater than the fan step register setting, the EMC2112 will lim it the fan drive change to the value of the fan step register. it will use the update time to determine how often to update the drive settings. application note: if the fan speed control algorithm is used, t he default settings in the fan configuration 2 register will cause the maximum fan step settings to be ignored. the fan step registers are software locked. 6.23 fan minimum drive register the fan minimum drive register stores the mini mum drive setting for each rpm-based fan speed control algorithm. the rpm-based fan speed control algorithm will not drive the fan at a level lower than the minimum drive unless the target fan speed is set at ffh (see section 6.26 ) during normal operation, if the fan stops for any reason (including low drive), the rpm-based fan speed control algorithm will attempt to restart the f an. setting the fan minimum drive registers to a setting that will maintain fan operat ion is a useful way to avoid potent ial fan oscillations as the control circuitry attempts to drive it at a level that cannot support fan operation. the fan minimum drive register is software locked. 6.24 valid tach count register the valid tach count register stores the maximu m tach reading register value to indicate that the each fan is spinning properly. the value is referenced at the end of the spin up routine to determine if the fan has started operating and decide if the device needs to retry. see equation [3] for translating the count to an rpm. this regist er is only used when the fsc is active. if the tach reading register value exceeds the valid tach count register (indicating that the fan rpm is below the threshold set by this count), then a stalled fan is detected. in this condition, the algorithm will automatically begin its spin up routine. if a tach target setting is set above the valid tach count setting, then that setting will be ignored and the algorithm will use the current fan drive setting. the valid tach count register is software locked. table 6.39 minimum fan drive register addrr/w register b7b6b5b4b3b2b1b0default 48h r/w fan minimum drive 128 64 32 16 8 4 2 1 66h (40%) table 6.40 valid tach count register addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default 49h r/w valid tach count 4096 2048 1024 512 256 128 64 32 f5h
rpm-based linear fan controller with hardware thermal shutdown datasheet smsc EMC2112 55 revision 0.88 (11-20-09) datasheet 6.25 fan drive fail band registers the fan drive fail band registers store the num ber of tach counts used by the fan drive fail detection circuitry. this circuitry is activated when the fan drive setting high byte is at ffh. when it is enabled, the actual measured fan speed is compar ed against the target fan speed. these registers are only used when the fsc is active. this circuitry is used to indicate that the target fan speed at full drive is higher than the fan is actually capable of reaching. if the measured fan speed does not exceed the target fan speed minus the fan drive fail band register settings for a period of time longer than set by the drive_fail_cntx[1:0] bits then the drive_fail status bit will be set and an interrupt generated. 6.26 tach target registers the tach target registers hold the target tachometer value that is maintained each of the rpm- based fan speed control algorithms. if one of the algorithms is enabled then setting the tach target register to ffh will disable the fan driver (set the fan drive setting to 0%). setting the tach target to any other value (from a setting of ffh) will cause the algorithm to invoke the spin up routine after which it will function normally. the tach target is not applied until the high byte is written. once the high byte is written, the current value of both high and low bytes will be used as the next tach target. 3 6.27 tach reading registers table 6.41 fan drive fail band registers addr r/w register b7b6b5b4b3b2b1b0default 4ah r/w fan drive fail band low byte 168421 - - - 00h 4bh r/w fan drive fail band high byte 4096 2048 1024 512 256 128 64 32 00h table 6.42 tach target registers addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default 4ch r/w tach target low byte 168421 - - - f8h 4dh r/w tach target high byte 4096 2048 1024 512 256 128 64 32 ffh table 6.43 tach reading registers addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default 4eh r fan tach 4096 2048 1024 512 256 128 64 32 ffh 4fh r fan tach low byte 168421 - - - f8h
rpm-based linear fan controller with hardware thermal shutdown datasheet revision 0.88 (11-20-09) 56 smsc EMC2112 datasheet the tach reading registers? contents describe the current tachometer readin g for each of the fan. by default, the data represents the fan speed as the number of 32khz clock periods that occur for a single revolution of the fan. equation [3] shows the detailed conversion from tach measurement (count) to rpm while equation [4] shows the simplified translation of tach readin g register count to rpm assuming a 2-pole fan, measuring 5 edges, with a frequency of 32.768khz. these equations ar e solved and tabulated for ease of use in an17.4 rpm to tach counts conversion. whenever the high byte register is read, the corresponding low byte data will be loaded to internal shadow registers so that when the low byte is r ead, the data will always coincide with the previously read high byte. bit 2 - idcf_5 - sets the bit state of idcfx bit 5. bit 1 - idcf_4 - sets the bit state of idcfx bit 4. bit 0 - idcf_3 - sets the bit state of idcfx bit 3. prior to enabling the run_all bit, the tatrim and type[ 1:0] bits must be set to the desired settings. 6.28 software lock register the software lock register controls the software locking of critical re gisters. this register is software locked. bit 0 - lock - this bit acts on all registers that ar e designated swl. when this bit is set, the locked registers become read on ly and cannot be updated. ? ?0? (default) - all swl registers can be updated normally. ? ?1? - all swl registers cannot be updated and a hard-reset is required to unlock them. where: [3] poles = number of poles of the fan (typically 2) f tach = the tachometer measurement frequen cy (typically 32.768khz) n = number of edges measured (typically 5 for a 2 pole fan) m = the multiplier defined by the range bits [4] count = tach reading register value (in decimal) table 6.44 software lock register addr r/w register b7 b6 b5 b4 b3 b2 b1 b0 default efh r/w software lock - - - - - - - lock 00h rpm 1 poles () -------------------- n 1 ? () count 1 m ---- - --------------------------------- - f tach 60 = rpm 3,932,160 m count -------------------------------------- =
rpm-based linear fan controller with hardware thermal shutdown datasheet smsc EMC2112 57 revision 0.88 (11-20-09) datasheet 6.29 product features register the product features register shows those func tions that are enabled by external pin states. bits 3-2 - adr[2:0] - indicates the selected smbus address as determined by the addr_sel pin. bits 1-0 - shdn_ch[1:0] - indicate s the selected temperatur e channel associated with the critical / thermal shutdown logic (see section 5.9 ). 6.30 product id register the product id register contains a uniq ue 8 bit word that identifies the product. table 6.45 product features register address r/w register b7 b6 b5 b4 b3 b2 b1 b0 default fch r product features - - - - adr[1:0] shdn_ch [1:0] 00h table 6.46 addr_sel pin configuration adr[1:0] slave address 10 0 0 0101_111xb 0 1 0111_101xb 1 0 0101_110xb table 6.47 shdn_ch pin configuration shdn_ch [1:0] hardware shutdown channel 10 0 0 external diode 1 measuring cpu / gpu diode 0 1 external diode 1 measuring amd or discrete diode 1 0 external diode 2 measuring discrete diode table 6.48 product id register address r/w register b7 b6 b5 b4 b3 b2 b1 b0 default fdh r product id 0 0 0 1 0 1 0 1 15h
rpm-based linear fan controller with hardware thermal shutdown datasheet revision 0.88 (11-20-09) 58 smsc EMC2112 datasheet 6.31 manufacturer id register the manufacturer id register contains a unique 8 bit word that identifies smsc. 6.32 revision register the revision register contains a 8 bit word that identifies the die revision. table 6.49 manufacturer id register address r/w register b7 b6 b5 b4 b3 b2 b1 b0 default feh r manufacturer id 010 1 1 1 0 1 5dh table 6.50 revision register address r/w register b7 b6 b5 b4 b3 b2 b1 b0 default ffh r revision 0 0 0 0 0 0 0 1 01h
rpm-based linear fan controller with hardware thermal shutdown datasheet smsc EMC2112 59 revision 0.88 (11-20-09) datasheet chapter 7 typical operating curves the following typical operating curves are included. ? supply current vs. temperature ? supply current vs. supply voltage ? temperature error vs. series resistance ? temperature error vs. c filter ? temperature error vs. ambient temperature ? temperature error vs. supply voltage ? tachometer measurement accuracy vs. temperature ? tachometer measurement a ccuracy vs. supply voltage ? high side drive voltage vs. temperature ? reset generator threshold vs. temperature ? reset generator threshold vs. supply voltage supply current vs. ambient temperature 1 1.05 1.1 1.15 1.2 1.25 0 20 40 60 80 100 120 140 ambient temperature (c) supply current (ma ) supply current vs. supply voltage 1 1.05 1.1 1.15 1.2 1.25 2.95 3.05 3.15 3.25 3.35 3.45 3.55 3.65 supply voltage (v) supply current (ma) -0.5 0 0.5 1 1.5 2 2.5 0 50 100 150 200 250 series resistance (ohm) 0 20 40 60 80 100 120 temperature error (c ? rec on) temperature error (c ? rec off) temperature error vs. series resistance rec on rec off temperature error vs. c filt er -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 0 1000 2000 3000 4000 5000 c filt er (pf) temperature error (c temperature error (c)
rpm-based linear fan controller with hardware thermal shutdown datasheet revision 0.88 (11-20-09) 60 smsc EMC2112 datasheet temperature error vs. ambient temperature -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 0 20 40 60 80 100 120 140 ambient temperature (c) temperature error ( c temperature error (c) ambient temperature (c) temperature error vs. supply voltage -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 2.95 3.05 3.15 3.25 3.35 3.45 3.55 3.65 supply voltage (v) temperature error ( c temperature error (c) tachometer measurement accuracy vs. ambient temperature 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 0 20 40 60 80 100 120 140 ambient temperuture (c) tach measurement accuracy (% internal clock external clock tach measurement accuracy (%) tachometer measurement accuracy vs. supply voltage 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 2.95 3.05 3.15 3.25 3.35 3.45 3.55 3.65 supply voltage (v) tach measurement accuracy (% external clock internal clock tach measurement accuracy (%) high side drive voltage vs. ambient temperature 4.9 4.91 4.92 4.93 4.94 4.95 4.96 4.97 4.98 4.99 5 0 20 40 60 80 100 120 140 ambient temperature (c) drive voltage (v) loaded (8.11ohm) unloaded (100kohm) reset generator threshold vs. ambient temperature 4.5 4.55 4.6 4.65 4.7 0 20 40 60 80 100 120 140 ambient temperature (c) reset generator threshold (v ) reset generator threshold (v)
rpm-based linear fan controller with hardware thermal shutdown datasheet smsc EMC2112 61 revision 0.88 (11-20-09) datasheet reset generator threshold vs. supply voltage 4.5 4.55 4.6 4.65 4.7 2.95 3.05 3.15 3.25 3.35 3.45 3.55 3.65 supply voltage (v) reset generator threshold (v reset generator threshold (v)
rpm-based linear fan controller with hardware thermal shutdown datasheet revision 0.88 (11-20-09) 62 smsc EMC2112 datasheet chapter 8 package outline 8.1 EMC2112 package drawin gs - 20-pin qfn 4mm x 4mm figure 8.1 EMC2112 package drawing - 20-pin qfn 4mm x 4mm
rpm-based linear fan controller with hardware thermal shutdown datasheet smsc EMC2112 63 revision 0.88 (11-20-09) datasheet figure 8.2 EMC2112 package dimensions and notes - 20-pin qfn 4mm x 4mm figure 8.3 EMC2112 pcb footprint - 20-pin qfn 4mm x 4mm
rpm-based linear fan controller with hardware thermal shutdown datasheet revision 0.88 (11-20-09) 64 smsc EMC2112 datasheet 8.2 package marking information figure 8.4 EMC2112 package markings bottom bottom marking not allowed line: 1 ? smsc logo without circled (r) symbol line: 2 ? device number line: 3 ? last 7 digits of lot number line: 4 ? revision and country code ( rcc) lines 1 to 3: center horizontal alignment line 4: left horizontal alignment pb-free/green symbol (matte sn) 0.41 3x 0.56 top c 2 m e 2 1 1 e3 pin 1 cc r 123456a
rpm-based linear fan controller with hardware thermal shutdown datasheet smsc EMC2112 65 revision 0.88 (11-20-09) datasheet chapter 9 datasheet revision history table 9.1 customer revision history revision level & date secti on/figure/entr y correction rev. 0.88 (11-20-09) figure 5.4, "EMC2112 critical/thermal shutdown block diagram" updated figure to show sys_shdn# is open drain. section 6.32, "revision register" updated value of revision register (ffh) from 00h to 01h to reflect the new die revision. chapter 7, typical operating curves added. rev. 0.87 (05-21-09) table 3.1, "absolute maximum ratings" updated ?junction to ambient?: from ?16 pin qfn? to ?20 pin qfn? note 3.2 (following table 3.1, "absolute maximum ratings" ) note modified: from ?ground plane with 3.1mm x 3.1mm? to ?ground plane with 2.6mm x 2.6mm? section 6.27, "tach reading registers" added reference to an17.4 table 3.2, "electrical specifications" updated electrical specifications for supply current, tach accuracy, and voh / vol conditions on digital pins rev. 0.85 (01-08-09) initial datasheet release

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